Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
1.0V
Symbol
Description
0.95V 0.9V Units
-3
-2/-2LE
-1
-1Q/-1M -1LI
-2LE
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG
CLK PREG to P output
0.33
0.52
0.37
0.59
0.44
0.69
0.44
0.69
0.44
0.69
0.54
0.84
ns
ns
TDSPCKO_CARRYCASCOUT_PREG
CLK PREG to
CARRYCASCOUT output
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK MREG to P output
1.68
1.92
1.93
2.21
2.31
2.64
2.31
2.64
2.31
2.64
2.73
3.12
ns
ns
TDSPCKO_CARRYCASCOUT_MREG
CLK MREG to
CARRYCASCOUT output
TDSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.72
2.96
3.10
3.38
3.69
4.02
3.69
4.02
3.69
4.02
4.60
4.99
ns
ns
TDSPCKO_CARRYCASCOUT_ADREG_
CLK ADREG to
CARRYCASCOUT output using
multiplier
MULT
Clock to Outs from Input Register Clock to Output Pins
CLK AREG to P output using
TDSPCKO_P_AREG_MULT
3.94
1.64
1.69
3.91
4.51
1.87
1.93
4.48
5.37
2.22
2.30
5.32
5.37
2.22
2.30
5.32
5.37
2.22
2.30
5.32
6.84
2.65
2.81
6.77
ns
ns
ns
ns
multiplier
TDSPCKO_P_BREG
CLK BREG to P output not using
multiplier
TDSPCKO_P_CREG
CLK CREG to P output not
using multiplier
TDSPCKO_P_DREG_MULT
CLK DREG to P output using
multiplier
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG;
BREG}
CLK (ACOUT, BCOUT) to {A,B}
register output
0.64
4.19
0.73
4.79
0.87
5.70
0.87
5.70
0.87
5.70
1.02
7.24
ns
ns
TDSPCKO_CARRYCASCOUT_{AREG,
BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
TDSPCKO_CARRYCASCOUT_ BREG
CLK BREG to
CARRYCASCOUT output not
using multiplier
1.88
4.16
1.94
2.15
4.76
2.21
2.55
5.65
2.63
2.55
5.65
2.63
2.55
5.65
2.63
3.04
7.17
3.20
ns
ns
ns
TDSPCKO_CARRYCASCOUT_
DREG_MULT
CLK DREG to
CARRYCASCOUT output using
multiplier
TDSPCKO_CARRYCASCOUT_ CREG
CLK CREG to
CARRYCASCOUT output
Maximum Frequency
FMAX
With all registers used
With pattern detector
628.93 550.66 464.25 464.25 464.25 363.77 MHz
531.63 465.77 392.93 392.93 392.93 310.08 MHz
349.28 305.62 257.47 257.47 257.47 210.44 MHz
FMAX_PATDET
FMAX_MULT_NOMREG
Two register multiply without
MREG
FMAX_MULT_NOMREG_PATDET
Two register multiply without
MREG with pattern detect
317.26 277.62 233.92 233.92 233.92 191.28 MHz
FMAX_PREADD_MULT_NOADREG
Without ADREG
397.30 346.26 290.44 290.44 290.44 223.26 MHz
397.30 346.26 290.44 290.44 290.44 223.26 MHz
FMAX_PREADD_MULT_NOADREG_
PATDET
Without ADREG with pattern
detect
DS181 (v1.25) June 18, 2018
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Product Specification
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