XC7A50T-2CSG325C 参数 Datasheet PDF下载

型号：	XC7A50T-2CSG325C
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 4075 CLBs, 1286MHz, 52160-Cell, CMOS, PBGA325, BGA-325]
分类和应用：	时钟栅可编程逻辑
文件页数/大小：	64 页 / 1094 K
品牌：	XILINX [ XILINX, INC ]

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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)

Speed Grade

Symbol

Description

1.0V

0.95V

-1LI

0.9V

-2LE

Units

-3

-2/-2LE

-1

-1Q/-1M

T_{RDCK_DI_ECC}

T_{RCKD_DI_ECC}

DIN inputs with block RAM 0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 0.63/0.50 0.78/0.54 ns, Min

ECC in standard mode⁽⁹⁾

T_{RDCK_DI_ECCW}

DIN inputs with block RAM 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 1.17/0.50 1.38/0.48 ns, Min

ECC encode only⁽⁹⁾

T_{RCKD_DI_ECCW}

T_{RDCK_DI_ECC_FIFO}

DIN inputs with FIFO ECC 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 1.32/0.64 1.55/0.77 ns, Min

in standard mode⁽⁹⁾

T_{RCKD_DI_ECC_FIFO}

T_{RCCK_INJECTBITERR}

T_{RCKC_INJECTBITERR}

Inject single/double bit

error in ECC mode

0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 0.74/0.40 0.92/0.48 ns, Min

T_{RCCK_EN}/T_{RCKC_EN}

Block RAM enable (EN)

input

0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 0.45/0.23 0.57/0.26 ns, Min

T_{RCCK_REGCE}

CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 0.36/0.16 0.40/0.19 ns, Min

T_{RCKC_REGCE}

T_{RCCK_RSTREG}

T_{RCKC_RSTREG}

Synchronous RSTREG

input

0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 0.35/0.07 0.41/0.07 ns, Min

0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 0.36/0.46 0.40/0.47 ns, Min

0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 0.54/0.20 0.64/0.23 ns, Min

0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 0.47/0.43 0.77/0.44 ns, Min

0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 0.43/0.43 0.71/0.50 ns, Min

T_{RCCK_RSTRAM}

T_{RCKC_RSTRAM}

Synchronous RSTRAM

input

T_{RCCK_WEA}

Write enable (WE) input

(block RAM only)

T_{RCKC_WEA}

T_{RCCK_WREN}

WREN FIFO inputs

T_{RCKC_WREN}

T_{RCCK_RDEN}

T_{RCKC_RDEN}

RDEN FIFO inputs

Reset Delays

T_{RCO_FLAGS}

Reset RST to FIFO

flags/pointers⁽¹⁰⁾

0.90

0.98

1.10

1.25

ns, Max

T_{RREC_RST}

FIFO reset recovery and 1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 2.37/–0.81 2.44/–0.71 ns, Max

removal timing⁽¹¹⁾

T_{RREM_RST}

Maximum Frequency

F_{MAX_BRAM_WF_NC}

Block RAM (write first and

no change modes) when

not in SDP RF mode

509.68

460.83

388.20

315.66

MHz

F_{MAX_BRAM_RF_}

PERFORMANCE

Block RAM (read first,

performance mode) when

in SDP RF mode but no

address overlap between

port A and port B

F_{MAX_BRAM_RF_}

DELAYED_WRITE

Block RAM (read first,

delayed write mode) when

in SDP RF mode and

there is possibility of

447.63

404.53

339.67

268.96

MHz

overlap between port A

and port B addresses

DS181 (v1.25) June 18, 2018

www.xilinx.com

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XC7A50T-2CSG325C 参数 Datasheet PDF下载

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