Spartan-3E FPGA Family: DC and Switching Characteristics
Table 119: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol Description
TCCS SPI serial Flash PROM chip-select time
Requirement
Units
ns
TCCS ≤ TMCCL1 – TCCO
TDSU
TDH
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
ns
ns
TDSU ≤ TMCCL1 – TCCO
TDH ≤ TMCCH 1
TV
ns
TV ≤ TMCCLn – TDCC
fC or fR
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
MHz
1
fC ≥ ------------------------------
TCCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
DS312 (v4.2) December 14, 2018
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