Spartan-3E FPGA Family: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/2005
11/23/2005
03/22/2006
Initial Xilinx release.
2.0
Added AC timing information and additional DC specifications.
3.0
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All speed grades
for all Spartan-3E FPGAs are now Production status using the v1.21 speed files, as shown in Table 84.
Expanded description in Note 2, Table 78. Updated pin-to-pin and clock-to-output timing based on final
characterization, shown in Table 86. Updated system-synchronous input setup and hold times based
on final characterization, shown in Table 87 and Table 88. Updated other I/O timing in Table 90.
Provided input and output adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards
that supersede the v1.21 speed file values, in Table 91 and Table 94. Reduced I/O three-state and
set/reset delays in Table 93. Added XC3S100E FPGA in CP132 package to Table 96. Increased TAS
slice flip-flop timing by 100 ps in Table 98. Updated distributed RAM timing in Table 99 and SRL16
timing in Table 100. Updated global clock timing, removed left/right clock buffer limits in Table 101.
Updated block RAM timing in Table 103. Added DCM parameters for remainder of Step 0 device;
added improved Step 1 DCM performance to Table 104, Table 105, Table 106, and Table 107. Added
minimum INIT_B pulse width specification, TINIT, in Table 111. Increased data hold time for Slave
Parallel mode to 1.0 ns (TSMCCD) in Table 117. Improved the DCM performance for the XC3S1200E,
Stepping 0 in Table 104, Table 105, Table 106, and Table 107. Corrected links in Table 118 and
Table 120. Added MultiBoot timing specifications to Table 122.
04/07/2006
05/19/2006
3.1
3.2
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP packages
(Table 97). Removed potentially confusing Note 2 from Table 78.
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards (Note 4,
Table 80). Other minor edits.
05/30/2006
11/09/2006
3.2.1
3.4
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in Table 73, providing additional overshoot
allowance. Widened the recommended voltage range for PCI and PCI-X standards in Table 80.
Clarified Note 2, Table 83. Improved various timing specifications for v1.26 speed file. Added Table 85
to summarize the history of speed file releases after which time all devices became Production status.
Added absolute minimum values for Table 86, Table 92, and Table 93. Updated pin-to-pin setup and
hold timing based on default IFD_DELAY_VALUE settings in Table 87, Table 88, and Table 90. Added
Table 89 about source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
03/16/2007
05/29/2007
3.5
3.6
Based on extensive 90 nm production data, improved (reduced) the maximum quiescent current limits
for the ICCINTQ, ICCAUXQ, and ICCOQ specifications in Table 79 by an average of 50%.
Added note to Table 74 and Table 75 regarding HSWAP in step 0 devices. Updated tRPW_CLB in
Table 98 to match value in speed file. Improved CLKOUT_FREQ_CLK90 to 200 MHz for Stepping 1 in
Table 105.
04/18/2008
3.7
Clarified that Stepping 0 was offered only for -4C and removed Stepping 0 -5 specifications. Added
reference to XAPP459 in Table 73 and Table 77. Improved recommended max VCCO to 3.465V (3.3V
+ 5%) in Table 77. Removed minimum input capacitance from Table 78. Updated Recommended
Operating Conditions for LVCMOS and PCI I/O standards in Table 80. Removed Absolute Minimums
from Table 86, Table 92 and Table 93 and added footnote recommending use of Timing Analyzer for
minimum values. Updated TPSFD and TPHFD in Table 87 to match current speed file. Update TRPW_IOB
in Table 88 to match current speed file and CLB equivalent spec. Added XC3S500E VQG100 to
Table 96. Replaced TMULCKID with TMSCKD for A, B, and P registers in Table 102. Updated
CLKOUT_PER_JITT_FX in Table 107. Updated MAX_STEPS equation in Table 109. Updated
Figure 77 and Table 120 to correct CCLK active edge. Updated links.
08/26/2009
3.8
Added reference to XAPP459 in Table 73 note 2. Updated BPI timing in Figure 77, Table 119, and
Table 120. Removed VREF requirements for differential HSTL and differential SSTL in Table 95. Added
Spread Spectrum paragraph. Revised hold times for TIOICKPD in Table 88 and setup times for TDICK in
Table 98. Added note 4 to Table 106 and note 3 to Table 107, and updated note 6 for Table 107 to add
input jitter.
DS312 (v4.2) December 14, 2018
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