Spartan-3E FPGA Family: DC and Switching Characteristics
Table 117: Timing for the Slave Parallel Configuration Mode (Cont’d)
All Speed Grades
Symbol
Description
Units
Min
Max
Clock Timing
TCCH
The High pulse width at the CCLK input pin
5
5
0
0
0
-
ns
TCCL
The Low pulse width at the CCLK input pin
-
ns
FCCPAR
Frequency of the clock signal No bitstream
Not using the BUSY pin(2)
Using the BUSY pin
50
66
20
MHz
MHz
MHz
at the CCLK input pin
compression
With bitstream compression
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
DS312 (v4.2) December 14, 2018
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Product Specification
149
XILINX [ XILINX, INC ]
