Spartan-3E FPGA Family: DC and Switching Characteristics
Configuration Clock (CCLK) Characteristics
Table 112: Master Mode CCLK Output Period by ConfigRate Option Setting
ConfigRate
Setting
Temperature
Range
Symbol
Description
Minimum
Maximum
Units
CCLK clock period by
ConfigRate setting
1
Commercial
570
ns
TCCLK1
(power-onvalueand
default value)
1,250
Industrial
Commercial
Industrial
485
285
242
142
121
71.2
60.6
35.5
30.3
17.8
15.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCCLK3
TCCLK6
TCCLK12
TCCLK25
3
625
313
157
78.2
39.1
Commercial
Industrial
6
Commercial
Industrial
12
25
50
Commercial
Industrial
Commercial
Industrial
TCCLK50
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in Module 2.
Table 113: Master Mode CCLK Output Frequency by ConfigRate Option Setting
ConfigRate
Setting
Temperature
Range
Symbol
Description
Minimum
Maximum
Units
Equivalent CCLK clock frequency
by ConfigRate setting
1
Commercial
1.8
MHz
FCCLK1
(power-onvalueand
default value)
0.8
Industrial
Commercial
Industrial
2.1
3.6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FCCLK3
FCCLK6
FCCLK12
FCCLK25
FCCLK50
3
1.6
3.2
4.2
Commercial
Industrial
7.1
6
8.3
Commercial
Industrial
14.1
16.5
28.1
33.0
56.2
66.0
12
25
50
6.4
Commercial
Industrial
12.8
25.6
Commercial
Industrial
Table 114: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
Symbol
Description
Units
1
3
6
12
25
50
TMCCL,
TMCCH
Master mode CCLK minimum
Low and High time
Commercial
Industrial
276
235
138
117
69
58
34.5
29.3
17.1
14.5
8.5
7.3
ns
ns
Table 115: Slave Mode CCLK Input Low and High Time
Symbol
Description
Min
Max
Units
TSCCL,
TSCCH
CCLK Low and High time
5
∞
ns
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
146
XILINX [ XILINX, INC ]
