Spartan-3E FPGA Family: DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 98: CLB (SLICEM) Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
-
0.52
-
0.60
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.46
1.58
-
-
0.52
1.81
-
-
ns
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
0
-
-
0
0
-
-
ns
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
0.70
0.70
0
-
-
0.80
0.80
0
-
-
ns
ns
TCL
FTOG
657
572
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
-
0.66
-
-
0.76
-
ns
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
1.57
1.80
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
DS312 (v4.2) December 14, 2018
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