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PZ3320N8YY 参数 Datasheet PDF下载

PZ3320N8YY图片预览
型号: PZ3320N8YY
PDF下载: 下载PDF文件 查看货源
内容描述: [LOADABLE PLD, 9.5ns, PBGA256, PLASTIC, BGA-256]
分类和应用: 时钟可编程逻辑
文件页数/大小: 32 页 / 488 K
品牌: XILINX [ XILINX, INC ]
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Philips Semiconductors  
Preliminary specification  
320 macrocell SRAM CPLD  
PZ3320C/PZ3320N  
PZ3320 has loaded its configuration data, it re-transmits incoming  
configuration data on dout. When used in daisy-chained operation,  
cclk is routed into all slave serial mode devices in parallel.  
Slave Serial Mode  
The slave serial mode is primarily used when multiple PZ3320s are  
configured in a daisy-chain. The serial slave serial mode is also  
used on the PZ3320 evaluation board, which interfaces to the  
download cable. A device in the slave serial mode can be used as  
the lead device in a daisy-chain. Figure 24 shows the interface for  
the slave serial configuration mode.  
Multiple slave PZ3320s can be loaded with identical configurations  
simultaneously. This is done by loading the configuration data into  
the din inputs in parallel.  
The configuration data is provided into the PZ3320’s din input  
synchronous with the configuration clock cclk input. After the  
TO DAISY–CHAINED  
DEVICES  
dout  
PZ3320  
initn  
prgmn  
done  
cclk  
MICRO–  
PROCESSOR  
OR  
DOWNLOAD  
CABLE  
data  
+3.3V  
M2  
M1  
M0  
SP00661  
Figure 24. Slave Serial Configuration Schematic  
BIT N – 1  
BIT N  
BIT N + 1  
DIN  
t
S
t
H
CCLK  
DOUT  
t
D
t
CL  
t
CH  
BIT N – 1  
BIT N  
BIT N + 1  
SP00610  
Figure 25. Slave Serial Configuration Mode Timing Diagram  
20  
1998 Jul 22  
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