Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
The generation of cclk for the daisy-chained devices which are in
slave serial mode differs depending on the configuration mode of the
lead device. A master parallel mode device uses its internal timing
generator to produce an internal cclk at eight times its memory
address rate (rclk). If the lead device is configured in either
synchronous peripheral, slave serial mode, or slave parallel mode,
cclk is routed to the lead device and to all of the daisy-chained
devices. The configuration data is read into din of slave devices on
the positive edge of cclk, and shifted out dout on the negative edge
of cclk.
DAISY CHAIN OPERATION
Multiple PZ3320s can be configured by using a daisy-chain of
PZ3320s. Daisy-chaining uses a lead PZ3320 and one or more
PZ3320s configured in slave serial mode. The lead PZ3320 can be
configured in any mode, but master parallel is typically used. Figure
28 shows the connections for loading multiple PZ3320s in a
daisy-chain configuration.
Daisy-chained PZ3320s are connected in series. An upstream
PZ3320 which has received the preamble outputs a high on dout
until it has received the appropriate number of data frames. This
ensures that downstream PZ3320s do not receive frame start bits.
After loading and re-transmitting the preamble to a daisy-chain of
slave devices, the lead device loads its configuration data frames.
The loading of configuration data continues after the lead device has
received its configuration data if the lead device’s internal frame bit
counter has not reached the length count. When the configuration
RAM is full and the number of bits received is less than the length
count field, the PZ3320 shifts data out on dout.
The development software can create a composite configuration file
for configuring daisy-chained PZ3320s. The configuration data
consists of multiple concatenated data packets. As seen in
Figure 28, the initn pins for all of the PZ3320s are connected
together. This is required to guarantee that power-up and
initialization function correctly. In general, the done pins for all of the
PZ3320s are also connected together as shown to guarantee that all
of the PZ3320s enter the start-up state simultaneously. This may not
be required, depending upon the start-up sequence desired.
cclk
cclk
din
cclk
dout
dout
dout
din
A[19:0]
A[19:0]
EEPROM
MASTER/LEAD
SLAVE #1
SLAVE #2
D[7:0]
D[7:0]
done
+3.3V
+3.3V
done
done
OE
CE
prgmn
prgmn
prgmn
+3.3V
+3.3V
initn
initn
initn
PROGRAM
M2
M1
M0
M2
M1
M0
+3.3V
or
GND
hdc
ldcn
rclk
hdc
ldcn
rclk
hdc
ldcn
rclk
M2
M1
M0
V
CC
SP00606
Figure 28. Daisy-chain Schematic
22
1998 Jul 22
XILINX [ XILINX, INC ]
