Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
CCLK
t
S
t
H
DIN
BIT N
t
D
DOUT
BIT N
SP00584
Figure 19. Master Serial Configuration Mode Timing Diagram
TO DAISY-CHAINED
DEVICES
dout
cclk
A[19:0]
D[7:0]
A[19:0]
D[7:0]
EEPROM
PZ3320
OE
CE
done
prgmn
PROGRAM
+3.3V
M2
M1
M0
V
OR GND
DD
SP00659
Figure 20. Master Parallel Configuration
A[19:0]
RCLK
t
CH
t
CL
t
S
t
H
D[7:0]
CCLK
DOUT
BYTE N
BYTE N + 1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
t
D
BYTE N
BYTE N + 1
SP00585
Figure 21. Master Parallel Configuration Mode Timing Diagram
18
1998 Jul 22
XILINX [ XILINX, INC ]
