Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
rising edge of cclk. The process repeats until all of the data is loaded
into the PZ3320. The serial data begins shifting out on dout 0.5
cycles after the parallel data was loaded. It requires additional cclks
after the last byte is loaded to complete the shifting. Figure 26
shows the interface for slave parallel mode.
Slave Parallel Mode
The slave parallel mode is essentially the same as the synchronous
peripheral mode, except that cs1 and cs0n do not need to be driven,
and there is no rdy_bsyn output. As in the synchronous peripheral
mode, byte-wide data is input into D[7:0] on the rising edge of the
cclk input. The first data byte is clocked in on the second cclk after
initn goes high. Subsequent data bytes are clocks in on every eighth
TO DAISY–CHAINED
DEVICES
dout
PZ3320
initn
MICRO–
PROCESSOR
OR
DOWNLOAD
CABLE
prgmn
done
cclk
8
D[7:0]
+3.3V
M2
M1
M0
SP00662
Figure 26. Slave Parallel Configuration Schematic
t
CH
CCLK
INIT
t
CL
t
H
t
S
D[7:0]
DOUT
BYTE 0
BYTE 1
D7
t
D
D0
D1
D2
D3
D4
D5
D6
D0
D1
SP00654
Figure 27. Slave Parallel Configuration Mode Timing Diagram
21
1998 Jul 22
XILINX [ XILINX, INC ]
