R
DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
03/01/05
11/23/05
03/22/06
Initial Xilinx release.
2.0
Added AC timing information and additional DC specifications.
3.0
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All
speed grades for all Spartan-3E FPGAs are now Production status using the v1.21 speed
files, as shown in Table 84. Expanded description in Note 2, Table 78. Updated pin-to-pin
and clock-to-output timing based on final characterization, shown in Table 86. Updated
system-synchronous input setup and hold times based on final characterization, shown in
Table 87 and Table 88. Updated other I/O timing in Table 90. Provided input and output
adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards that supersede
the v1.21 speed file values, in Table 91 and Table 94. Reduced I/O three-state and set/reset
delays in Table 93. Added XC3S100E FPGA in CP132 package to Table 96. Increased T
AS
slice flip-flop timing by 100 ps in Table 98. Updated distributed RAM timing in Table 99 and
SRL16 timing in Table 100. Updated global clock timing, removed left/right clock buffer limits
in Table 101. Updated block RAM timing in Table 103. Added DCM parameters for
remainder of Step 0 device; added improved Step 1 DCM performance to Table 104,
Table 105, Table 106, and Table 107. Added minimum INIT_B pulse width specification,
T
, in Table 111. Increased data hold time for Slave Parallel mode to 1.0 ns (T
) in
INIT
SMCCD
Table 117. Improved the DCM performance for the XC3S1200E, Stepping 0 in Table 104,
Table 105, Table 106, and Table 107. Corrected links in Table 118 and Table 120. Added
MultiBoot timing specifications to Table 122.
04/07/06
05/19/06
3.1
3.2
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP
packages (Table 97). Removed potentially confusing Note 2 from Table 78.
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards
(Note 4, Table 80). Other minor edits.
05/30/06
11/09/06
3.2.1
3.4
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in Table 73, providing additional
overshoot allowance. Widened the recommended voltage range for PCI and PCI-X
standards in Table 80. Clarified Note 2, Table 83. Improved various timing specifications for
v1.26 speed file. Added Table 85 to summarize the history of speed file releases after which
time all devices became Production status. Added absolute minimum values for Table 86,
Table 92, and Table 93. Updated pin-to-pin setup and hold timing based on default
IFD_DELAY_VALUE settings in Table 87, Table 88, and Table 90. Added Table 89 about
source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
03/16/07
05/29/07
3.5
3.6
Based on extensive 90 nm production data, improved (reduced) the maximum quiescent
current limits for the I
of 50%.
, I
, and I
specifications in Table 79 by an average
CCINTQ CCAUXQ
CCOQ
Added note to Table 74 and Table 75 regarding HSWAP in step 0 devices. Updated
in Table 98 to match value in speed file. Improved CLKOUT_FREQ_CLK90 to 200
t
RPW_CLB
MHz for Stepping 1 in Table 105.
DS312-3 (v3.8) August 26, 2009
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Product Specification
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