R
DC and Switching Characteristics
Table 121: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
Description
Requirement
Units
T
(t
Parallel NOR Flash PROM chip-select
time
ns
CE
TCE ≤ TINITADDR
)
ELQV
T
(t
Parallel NOR Flash PROM
output-enable time
ns
ns
ns
OE
TOE ≤ TINITADDR
)
)
GLQV
T
Parallel NOR Flash PROM read access
time
TACC ≤ 0.5TCCLKn(min) – TCCO – TDCC – PCB
ACC
(t
AVQV
T
(t
For x8/x16 PROMs only: BYTE# to
BYTE
TBYTE ≤ TINITADDR
(3)
t
)
output valid time
FLQV, FHQV
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
Table 122: MultiBoot Trigger (MBT) Timing
Symbol
Description
Minimum
Maximum
Units
T
MultiBoot Trigger (MBT) Low pulse width required to initiate
MultiBoot reconfiguration
300
∞
ns
MBT
Notes:
1. MultiBoot re-configuration starts on the rising edge after MBT is Low for at least the prescribed minimum period.
DS312-3 (v3.8) August 26, 2009
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Product Specification
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