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Spartan-3E FPGA Family:
Pinout Descriptions
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DS312-4 (v3.8) August 26, 2009
Product Specification
Introduction
This section describes the various pins on a Spartan®-3E
FPGA and how they connect within the supported compo-
nent packages.
Pin Types
Most pins on a Spartan-3E FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 11 different
functional types of pins on Spartan-3E packages, as out-
lined in Table 124. In the package footprint drawings that fol-
low, the individual pins are color-coded according to pin
type as in the table.
Table 124: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired
together to form differential I/Os.
IO
IO_Lxxy_#
INPUT
DUAL
Unrestricted, general-purpose input-only pin. This pin does not have an
output structure, differential termination resistor, or PCI clamp diode.
IP
IP_Lxxy_#
Dual-purpose pin used in some configuration modes during the
configuration process and then usually available as a user I/O after
configuration. If the pin is not used during configuration, this pin behaves
as an I/O-type pin. Some of the dual-purpose pins are also shared with
bottom-edge global (GCLK) or right-half (RHCLK) clock inputs. See the
Configuration section in Module 2 for additional information on these
signals.
M[2:0]
HSWAP
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF
CLK
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along
with all other VREF pins in the same bank, provides a reference voltage
input for certain I/O standards. If used for a reference voltage within a bank, IO/VREF_#
IP/VREF_#
IP_Lxxy_#/VREF_#
all VREF pins within the bank must be connected.
IO_Lxxy_#/VREF_#
Either a user-I/O pin or Input-only pin, or an input to a specific clock buffer IO_Lxxy_#/GCLK[15:10, 7:2]
driver. Every package has 16 global clock inputs that optionally clock the
entire device. The RHCLK inputs optionally clock the right-half of the
IP_Lxxy_#/GCLK[9:8, 1:0]
IO_Lxxy_#/LHCLK[7:0]
device. The LHCLK inputs optionally clock the left-half of the device. Some IO_Lxxy_#/RHCLK[7:0]
of the clock pins are shared with the dual-purpose configuration pins and
are considered DUAL-type. See the Clocking Infrastructure section in
Module 2 for additional information on these signals.
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Product Specification
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