R
DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
PROG_B
(Input)
HSWAP
(Input)
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
M[2:0]
(Input)
<0:1:0>
TMINIT
TINITM
INIT_B
(Open-Drain)
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
LDC[2:0]
HDC
CSO_B
New ConfigRate active
TCCLK1
TCCLKn
TINITADDR
TCCLK1
CCLK
TCCO
000_0000
Address
Address Address
TCCD
A[23:0]
000_0001
T
TDCC
Data
AVQV
D[7:0]
(Input)
Byte 0
Data
Data
Data
Byte 1
Shaded values indicate specifications on attached parallel NOR Flash PROM.
DS312-3_08_032409
Figure 78: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Table 120: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
Description
Minimum Maximum
See Table 112
Units
T
Initial CCLK clock period
CCLK1
CCLKn
MINIT
T
T
CCLK clock period after FPGA loads ConfigRate setting
See Table 112
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
50
0
-
ns
ns
T
T
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
-
INITM
BPI-UP:
(M[2:0]=<0:1:0>)
Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
5
2
5
2
T
CCLK1
cycles
INITADDR
BPI-DN:
(M[2:0]=<0:1:1>)
T
T
T
Address A[23:0] outputs valid after CCLK falling edge
See Table 116
See Table 116
See Table 116
CCO
DCC
CCD
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
158
www.xilinx.com
DS312-3 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
