R
Pinout Descriptions
lar, as shown in the mechanical drawings provided in
Table 127.
Package Overview
Table 125 shows the eight low-cost, space-saving produc-
tion package styles for the Spartan-3E family. Each pack-
age style is available as a standard and an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For exam-
ple, the standard “VQ100” package becomes “VQG100”
when ordered as the Pb-free option. The mechanical
dimensions of the standard and Pb-free packages are simi-
Not all Spartan-3E densities are available in all packages.
For a specific package, however, there is a common foot-
print that supports all the devices available in that package.
See the footprint diagrams that follow.
For additional package information, see UG112: Device
Package User Guide.
Table 125: Spartan-3E Family Package Options
Lead
Pitch
(mm)
Maximum
I/O
Footprint
Area (mm)
Height
(mm)
Mass(1)
(g)
Package
Leads
100
132
144
208
256
320
400
484
Type
VQ100 / VQG100
CP132 / CPG132
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
Very-thin Quad Flat Pack (VQFP)
Chip-Scale Package (CSP)
66
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
16 x 16
8.1 x 8.1
22 x 22
1.20
1.10
1.60
4.10
1.55
2.00
2.43
2.60
0.6
0.1
1.4
5.3
0.9
1.4
2.2
2.2
92
Thin Quad Flat Pack (TQFP)
Plastic Quad Flat Pack (PQFP)
Fine-pitch, Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
108
158
190
250
304
376
30.6 x 30.6
17 x 17
19 x 19
21 x 21
23 x 23
Notes:
1. Package mass is 10%.
packages are superior in almost every other aspect, as
summarized in Table 126. Consequently, Xilinx recom-
mends using BGA packaging whenever possible.
Selecting the Right Package Option
Spartan-3E FPGAs are available in both quad-flat pack
(QFP) and ball grid array (BGA) packaging options. While
QFP packaging offers the lowest absolute cost, the BGA
Table 126: QFP and BGA Comparison
Characteristic
Quad Flat Pack (QFP)
Ball Grid Array (BGA)
Maximum User I/O
158
Good
Fair
376
Better
Better
Better
Better
4-6
Packing Density (Logic/Area)
Signal Integrity
Simultaneous Switching Output (SSO) Support
Thermal Dissipation
Fair
Fair
Minimum Printed Circuit Board (PCB) Layers
Hand Assembly/Rework
4
Possible
Difficult
DS312-4 (v3.8) August 26, 2009
www.xilinx.com
165
Product Specification
XILINX [ XILINX, INC ]
