R
DC and Switching Characteristics
Date
Version
Revision
04/18/08
3.7
Clarified that Stepping 0 was offered only for -4C and removed Stepping 0 -5 specifications.
Added reference to XAPP459 in Table 73 and Table 77. Improved recommended max V
CCO
to 3.465V (3.3V + 5%) in Table 77. Removed minimum input capacitance from Table 78.
Updated Recommended Operating Conditions for LVCMOS and PCI I/O standards in
Table 80. Removed Absolute Minimums from Table 86, Table 92 and Table 93 and added
footnote recommending use of Timing Analyzer for minimum values. Updated T
and
PSFD
T
in Table 87 to match current speed file. Update T
in Table 88 to match
PHFD
RPW_IOB
current speed file and CLB equivalent spec. Added XC3S500E VQG100 to Table 96.
Replaced T with T for A, B, and P registers in Table 102. Updated
MULCKID
MSCKD
CLKOUT_PER_JITT_FX in Table 107. Updated MAX_STEPS equation in Table 109.
Updated Figure 78 and Table 120 to correct CCLK active edge. Updated links.
08/26/09
3.8
Added reference to XAPP459 in Table 73 note 2. Updated BPI timing in Figure 78,
Table 119, and Table 120. Removed V
requirements for differential HSTL and differential
REF
SSTL in Table 95. Added Spread Spectrum paragraph. Revised hold times for T
in
IOICKPD
Table 88 and setup times for T
in Table 98. Added note 4 to Table 106 and note 6 to
DICK
Table 107, and updated note 6 for Table 107 to add input jitter.
162
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DS312-3 (v3.8) August 26, 2009
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