Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 40: CLB Distributed RAM Switching Characteristics (SLICEM Only)
Speed Grade
Symbol
Description
Units
-4
-3
-2
-1L
Sequential Delays
TSHCKO
Clock to A – D outputs
Clock to A – D outputs (direct output path)
Setup and Hold Times Before/After Clock CLK
1.26
0.96
1.55
1.20
2.12
1.60
2.56
ns, Max
ns, Max
T
DS/TDH
AS/TAH
TWS/TWH
CECK/TCKCE
AX – DX or AI – DI inputs to CLK
Address An inputs to clock
WE input to clock
0.59
0.17
0.73
0.22
1.04
0.37
1.17
0.33
ns, Min
ns, Min
ns, Min
ns, Min
T
0.28
0.35
0.32
0.42
0.40
0.67
0.26
0.71
0.31
–0.08
0.37
–0.08
0.59
–0.08
0.59
–0.27
T
CE input to CLK
0.31
–0.08
0.37
–0.08
0.59
–0.08
0.59
–0.27
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 41: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
Units
-4
-3
-2
-1L
Sequential Delays
TREG
Clock to A – D outputs
Clock to A – D outputs (direct output path)
Setup and Hold Times Before/After Clock CLK
1.35
1.24
1.78
1.65
2.14
1.95
2.89
ns, Max
ns, Max
T
WS/TWH
WE input to CLK
0.20
–0.07
0.24
–0.07
0.36
–0.07
0.59
–0.17
ns, Min
ns, Min
ns, Min
T
CECK/TCKCE
CE input to CLK
0.27
0.36
0.29
0.38
0.52
0.40
0.59
–0.17
TDS/TDH
AX – DX or AI – DI inputs to CLK
0.07
0.11
0.09
0.14
0.18
0.28
1.16
0.28
DS162 (v1.9) August 23, 2010
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Advance Product Specification
40
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