Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 36: ISERDES2 Switching Characteristics
Speed Grade
Symbol
Description
Units
-4
-3
-2
-1L
Setup/Hold for Control Lines
T
ISCCK_BITSLIP/ TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK
0.16
–0.09
0.20
–0.09
0.31
–0.09
0.34
–0.14
ns
ns
T
ISCCK_CE / TISCKC_CE
0.71
–0.47
0.71
–0.42
0.97
–0.42
1.39
–0.71
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.24
–0.15
0.25
–0.05
0.29
–0.05
0.12
–0.06
ns
ns
ns
ns
T
T
ISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IODELAY2)
–0.25
0.30
–0.25
0.42
–0.25
0.56
–0.54
0.67
ISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at DDR mode
–0.03
0.04
–0.03
0.16
–0.03
0.18
–0.05
0.12
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR
/
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY2)
–0.40
0.48
–0.40
0.53
–0.40
0.71
–0.71
0.86
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
1.30
1.44
2.02
2.22
ns
Output Serializer/Deserializer Switching Characteristics
Table 37: OSERDES2 Switching Characteristics
Speed Grade
Symbol
Description
Units
-4
-3
-2
-1L
Setup/Hold
OSDCK_D/TOSCKD_D
T
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
OCE input Setup/Hold with respect to CLK
TCE input Setup/Hold with respect to CLK
–0.03
1.02
–0.03
1.17
–0.03
1.27
–0.02
0.23
ns
ns
ns
ns
(1)
TOSDCK_T/TOSCKD_T
–0.05
1.03
–0.05
1.13
–0.05
1.23
–0.05
0.24
TOSCCK_OCE/TOSCKC_OCE
0.12
–0.03
0.15
–0.03
0.24
–0.03
0.28
–0.17
TOSCCK_TCE/TOSCKC_TCE
0.14
–0.08
0.17
–0.08
0.27
–0.08
0.31
–0.16
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
Clock to out from CLK to TQ
0.94
0.94
1.11
1.11
1.51
1.51
1.89
1.91
ns
ns
TOSCKO_TQ
Notes:
1.
T
/T
(T input setup/hold with respect to CLKDIV) are reported as T
/T
in TRACE report.
OSDCK_T2 OSCKD_T2
OSDCK_T OSCKD_T
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
37
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