Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 43: DSP48A1 Switching Characteristics (Cont’d)
Speed Grade
Pre-
Post-
Symbol
Description
Multiplier
Units
adder
adder
-4
-3
-2
-1L
1.90
5.83
Clock to Out from Output Register Clock to Output Pin
TDSPCKO_P_PREG CLK (PREG) to P output
Clock to Out from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG CLK (MREG) to P output
Clock to Out from Input Register Clock to Output Pins
N/A
N/A
N/A
N/A
N/A
Yes
1.20
3.38
1.34
3.95
1.34
4.19
ns
ns
TDSPCKO_P_A1REG
TDSPCKO_P_B1REG
TDSPCKO_P_CREG
TDSPCKO_P_DREG
CLK (A1REG) to P output
CLK (B1REG) to P output
CLK (CREG) to P output
CLK (DREG) to P output
N/A
N/A
N/A
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
Yes
5.02
5.02
3.12
6.77
5.87
5.87
3.64
7.92
6.80
6.79
3.70
9.06
9.65
9.63
ns
ns
ns
ns
5.24
12.53
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_P
A input to P output
N/A
N/A
N/A
Yes
Yes
Yes
N/A
Yes
Yes
No
No
Yes
Yes
No
Yes
No
2.85
3.35
4.56
3.22
6.01
6.27
2.69
6.31
6.43
4.84
3.11
3.33
3.93
5.22
3.76
6.54
7.34
3.15
7.38
7.52
5.66
3.49
3.41
4.83
6.38
3.91
6.88
8.43
3.30
8.32
8.35
6.52
3.55
4.73
6.74
8.94
5.55
9.76
11.96
4.68
11.81
11.84
9.25
5.03
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Yes
No
TDSPDO_B_P
B input to P output
Yes
Yes
N/A
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
TDSPDO_C_P
C input to P output
TDSPDO_D_P
D input to P output
TDSPDO_OPMODE_P
OPMODE input to P output
No
Maximum Frequency
FMAX
All registers used
Yes
Yes
Yes
390
333
302
213
MHz
Notes:
1. A Yes signifies that the component is in the path. A No signifies that the component is being bypassed. N/A signifies not applicable because no path
exists.
DS162 (v1.9) August 23, 2010
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Advance Product Specification
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