Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 34: ILOGIC2 Switching Characteristics
Symbol Description
Setup/Hold
Speed Grade
Units
-4
-3
-2
-1L
T
T
T
T
ICE0CK/TICKCE0
ISRCK/TICKSR
IDOCK/TIOCKD
IDOCKD/TIOCKDD
CE0 pin Setup/Hold with respect to CLK
0.56
–0.30
0.56
–0.25
0.79
–0.22
1.24
–0.55
ns
ns
ns
ns
SR pin Setup/Hold with respect to CLK
0.74
–0.23
0.74
–0.22
0.98
–0.20
1.35
–0.49
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY2)
1.19
–0.83
1.36
–0.83
1.73
–0.83
1.97
–1.09
0.31
0.00
0.47
0.00
0.54
0.00
0.64
–0.16
Combinatorial
TIDI
D pin to O pin propagation delay, no Delay
0.95
0.23
1.28
0.39
1.53
0.44
1.97
0.64
ns
ns
TIDID
DDLY pin to O pin propagation delay (using IODELAY2)
Sequential Delays
TIDLO
D pin to Q pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2)
CLK to Q outputs
1.56
0.68
1.03
1.81
1.86
0.97
1.24
1.81
2.39
1.20
1.43
2.50
3.22
1.89
1.66
3.05
ns
ns
ns
ns
TIDLOD
TICKQ
TRQ_ILOGIC2
SR pin to Q outputs
Table 35: OLOGIC2 Switching Characteristics
Symbol Description
Speed Grade
Units
-4
-3
-2
-1L
Setup/Hold
ODCK/TOCKD
T
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
0.60
–0.05
0.86
–0.05
1.18
0.00
1.15
–0.26
ns
ns
ns
ns
ns
T
OOCECK/TOCKOCE
TOSRCK/TOCKSR
OTCK/TOCKT
OTCECK/TOCKTCE
0.75
–0.10
0.75
–0.10
1.01
–0.05
0.56
–0.22
0.68
–0.28
0.79
–0.28
1.03
–0.23
1.09
–0.46
T
0.24
–0.08
0.56
–0.06
0.83
–0.01
0.86
–0.18
T
0.58
–0.06
0.72
–0.06
1.18
–0.01
0.47
–0.12
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.55
1.81
0.51
1.81
0.74
2.50
0.97
3.05
ns
ns
TRQ_OLOGIC2
SR pin to OQ/TQ out
DS162 (v1.9) August 23, 2010
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Advance Product Specification
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