Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DSP48A1 Switching Characteristics
Table 43: DSP48A1 Switching Characteristics
Speed Grade
Pre-
adder
Post-
adder
Symbol
Description
Multiplier
Units
-4
-3
-2
-1L
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_A1REG
TDSPCKD_A_A1REG
/
A input to A1 register CLK
D input to B1 register CLK
C input to C register CLK
D input to D register CLK
N/A
Yes
N/A
N/A
Yes
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.15
0.09
0.17
0.09
0.23
0.09
0.32
0.09
ns
ns
ns
ns
ns
ns
TDSPDCK_D_B1REG
TDSPCKD_D_B1REG
/
1.90
1.95
1.99
2.82
–0.07 –0.07 –0.07 –0.07
TDSPDCK_C_CREG
TDSPCKD_C_CREG
/
/
0.11
0.15
0.13
0.15
0.17
0.15
0.24
0.09
TDSPDCK_D_DREG
TDSPCKD_D_DREG
0.09
0.15
0.10
0.15
0.14
0.15
0.19
0.12
TDSPDCK_OPMODE_B1REG
TDSPCKD_OPMODE_B1REG
/
OPMODE input to B1
register CLK
1.97
0.01
2.00
0.01
2.01
0.01
2.85
0.01
T
DSPDCK_OPMODE_OPMODEREG/ OPMODE input to
0.18
0.12
0.21
0.12
0.28
0.26
0.40
0.12
TDSPCKD_OPMODE_OPMODEREG OPMODE register CLK
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_A_MREG
TDSPCKD_A_MREG
/
A input to M register CLK
B input to M register CLK
D input to M register CLK
N/A
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
N/A
N/A
N/A
N/A
N/A
3.06
3.51
3.71
3.97
ns
ns
ns
ns
ns
–0.40 –0.40 –0.40 –0.40
TDSPDCK_B_MREG
TDSPCKD_B_MREG
/
3.96
4.58
5.28
7.00
–0.68 –0.68 –0.68 –0.68
TDSPDCK_D_MREG
TDSPCKD_D_MREG
/
4.23 4.80 4.82 6.84
–0.56 –0.56 –0.56 –0.56
TDSPDCK_OPMODE_MREG
TDSPCKD_OPMODE_MREG
/
OPMODE to M register
CLK
4.18 4.80 4.85 6.88
–0.48 –0.48 –0.48 –0.48
2.37 2.70 3.02 4.28
–0.48 –0.48 –0.48 –0.48
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_A_PREG
TDSPCKD_A_PREG
/
A input to P register CLK
N/A
Yes
No
Yes
Yes
Yes
N/A
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
4.32
5.06
5.38
7.52
ns
ns
ns
ns
ns
ns
ns
ns
–0.76 –0.76 –0.76 –0.76
TDSPDCK_B_PREG
TDSPCKD_B_PREG
/
B input to P register CLK
5.87 6.87 7.87 10.55
–0.59 –0.59 –0.59 –0.59
4.14 4.68 6.16 8.12
–0.93 –0.93 –0.93 –0.93
2.20 2.25 2.30 3.27
TDSPDCK_C_PREG
TDSPCKD_C_PREG
/
/
C input to P register CLK
D input to P register CLK
N/A
Yes
Yes
No
–0.23 –0.23 –0.23 –0.23
TDSPDCK_D_PREG
TDSPCKD_D_PREG
5.90 6.91 7.32 10.39
–0.92 –0.92 –0.92 –0.92
6.21 7.27 7.35 10.43
TDSPDCK_OPMODE_PREG
TDSPCKD_OPMODE_PREG
/
OPMODE input to P
register CLK
–0.84 –0.84 –0.84 –0.84
1.69 1.98 2.55 3.62
–0.87 –0.87 –0.87 –0.87
2.09 2.30 2.67 3.79
No
–0.22 –0.22 –0.22 –0.22
DS162 (v1.9) August 23, 2010
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