Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 33: SSO Limit per VCCO/GND Pair (Cont’d)
SSO Limit per V
/GND Pair
CCO
All TQG144, CPG196,
CSG225, FT(G)256, and
LX devices in CSG324
All CSG484, FG(G)484,
FG(G)676, FG(G)900, and
LXT devices in CSG324
V
I/O Standard
Drive
Slew
CCO
Bank 0/2
Bank 1/3
65
80
89
30
41
49
21
28
39
16
22
28
3
Bank 0/2
Bank 1/3/4/5
Fast
53
70
79
23
34
44
16
21
34
12
16
27
1
53
70
79
23
34
44
16
21
34
12
16
27
1
62
73
91
27
37
46
20
25
34
15
19
24
1
2
4
Slow
QuietIO
Fast
Slow
QuietIO
Fast
6
Slow
QuietIO
Fast
LVTTL
8
Slow
QuietIO
Fast
12
16
24
Slow
2
5
2
4
3.3V
QuietIO
Fast
2
10
3
2
8
1
1
1
Slow
1
7
1
2
QuietIO
Fast
3
11
2
3
8
1
1
1
Slow
2
5
2
2
QuietIO
8
9
8
8
PCI33_3
PCI66_3
SSTL_3_I
SSTL_3_II
18
18
5
19
19
8
18
18
5
19
19
8
3
5
3
3
DIFF_SSTL_3_I
DIFF_SSTL_3_II
SDIO
15
9
24
15
18
15
9
24
9
17
17
15
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
34
XILINX [ XILINX, INC ]
