Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 33: SSO Limit per VCCO/GND Pair (Cont’d)
SSO Limit per V
/GND Pair
CCO
All TQG144, CPG196,
CSG225, FT(G)256, and
LX devices in CSG324
All CSG484, FG(G)484,
FG(G)676, FG(G)900, and
LXT devices in CSG324
V
I/O Standard
Drive
Slew
CCO
Bank 0/2
38
46
57
21
26
33
15
19
25
12
15
21
1
Bank 1/3
Bank 0/2
38
46
57
21
26
33
15
19
25
12
15
21
1
Bank 1/3/4/5
Fast
43
52
64
24
31
32
17
22
23
15
18
19
3
43
48
59
23
27
30
16
19
19
14
16
16
1
2
4
Slow
QuietIO
Fast
Slow
QuietIO
Fast
6
Slow
QuietIO
Fast
LVCMOS25
8
Slow
QuietIO
Fast
2.5V
12
16
24
Slow
2
7
2
4
QuietIO
Fast
3
8
3
8
1
3
1
1
Slow
3
7
3
3
QuietIO
Fast
4
9
4
8
N/A
N/A
N/A
10
N/A
30
N/A
3
N/A
N/A
N/A
10
N/A
30
N/A
1
Slow
5
2
QuietIO
8
6
SSTL_2_I (3)
SSTL_2_II (3)
DIFF_SSTL_2_I (3)
DIFF_SSTL_2_II (3)
11
7
11
7
33
21
33
24
DS162 (v1.9) August 23, 2010
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Advance Product Specification
32
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