Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 33: SSO Limit per VCCO/GND Pair (Cont’d)
SSO Limit per V
/GND Pair
CCO
All TQG144, CPG196,
CSG225, FT(G)256, and
LX devices in CSG324
All CSG484, FG(G)484,
FG(G)676, FG(G)900, and
LXT devices in CSG324
V
I/O Standard
Drive
Slew
CCO
Bank 0/2
33
Bank 1/3
40
62
67
21
30
33
16
19
24
13
16
20
5
Bank 0/2
33
Bank 1/3/4/5
Fast
41
56
66
21
24
30
16
17
21
12
14
17
4
2
4
Slow
57
57
QuietIO
Fast
70
70
19
19
Slow
30
30
QuietIO
Fast
38
38
14
14
6
Slow
18
18
QuietIO
Fast
27
27
LVCMOS15, LVCMOS15_JEDEC
11
11
8
Slow
16
16
QuietIO
Fast
23
23
N/A
N/A
N/A
N/A
N/A
N/A
9
N/A
N/A
N/A
N/A
N/A
N/A
9
1.5V
12
16
Slow
8
5
QuietIO
Fast
10
5
9
4
Slow
8
8
QuietIO
10
10
5
9
HSTL_I
10
6
HSTL_II
N/A
7
N/A
7
HSTL_III
9
9
DIFF_HSTL_I
DIFF_HSTL_II
DIFF_HSTL_III
SSTL_15_II (3)
DIFF_SSTL_15_II (3)
27
30
15
27
5
27
30
18
27
4
N/A
21
N/A
21
N/A
N/A
N/A
N/A
15
12
DS162 (v1.9) August 23, 2010
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Advance Product Specification
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