Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 33: SSO Limit per VCCO/GND Pair (Cont’d)
SSO Limit per V
/GND Pair
CCO
All TQG144, CPG196,
CSG225, FT(G)256, and
LX devices in CSG324
All CSG484, FG(G)484,
FG(G)676, FG(G)900, and
LXT devices in CSG324
V
I/O Standard
Drive
Slew
CCO
Bank 0/2
39
65
80
22
38
45
16
27
30
13
16
25
5
Bank 1/3
46
75
80
25
36
40
18
25
28
15
18
22
7
Bank 0/2
39
65
80
22
38
45
16
27
30
13
16
25
5
Bank 1/3/4/5
Fast
47
74
85
25
29
35
17
19
23
14
16
18
5
2
4
Slow
QuietIO
Fast
Slow
QuietIO
Fast
6
Slow
QuietIO
Fast
LVCMOS18, LVCMOS18_JEDEC
8
Slow
QuietIO
Fast
12
16
24
Slow
7
8
7
6
QuietIO
Fast
11
4
10
5
11
4
8
4
1.8V
Slow
7
8
7
5
QuietIO
Fast
11
N/A
N/A
N/A
9
10
5
11
N/A
N/A
N/A
9
8
3
Slow
8
8
QuietIO
10
10
5
8
HSTL_I_18
9
HSTL_II_18
N/A
9
N/A
9
6
HSTL_III_18
10
30
15
30
14
42
10
5
11
27
18
33
14
42
10
4
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
MOBILE_DDR (3)
DIFF_MOBILE_DDR (3)
SSTL_18_I (3)
SSTL_18_II (3)
DIFF_SSTL_18_I (3)
DIFF_SSTL_18_II (3)
27
N/A
27
12
36
9
27
N/A
27
12
36
9
N/A
27
N/A
N/A
27
N/A
30
15
30
12
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
31
XILINX [ XILINX, INC ]
