R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Multiplier Switching Characteristics
Table 24: Multiplier Switching Characteristics
Speed Grade
Description
Propagation Delay to Output Pin
Input to Pin 35
Input to Pin 34
Input to Pin 33
Input to Pin 32
Input to Pin 31
Input to Pin 30
Input to Pin 29
Input to Pin 28
Input to Pin 27
Input to Pin 26
Input to Pin 25
Input to Pin 24
Input to Pin 23
Input to Pin 22
Input to Pin 21
Input to Pin 20
Input to Pin 19
Input to Pin 18
Input to Pin 17
Input to Pin 16
Input to Pin 15
Input to Pin 14
Input to Pin 13
Input to Pin 12
Input to Pin 11
Input to Pin 10
Input to Pin 9
Symbol
-6
-5
-4
Units
TMULT_P35
TMULT_P34
TMULT_P33
TMULT_P32
TMULT_P31
TMULT_P30
TMULT_P29
TMULT_P28
TMULT_P27
TMULT_P26
TMULT_P25
TMULT_P24
TMULT_P23
TMULT_P22
TMULT_P21
TMULT_P20
TMULT_P19
TMULT_P18
TMULT_P17
TMULT_P16
TMULT_P15
TMULT_P14
TMULT_P13
TMULT_P12
TMULT_P11
TMULT_P10
TMULT_P9
TMULT_P8
TMULT_P7
TMULT_P6
TMULT_P5
TMULT_P4
TMULT_P3
TMULT_P2
TMULT_P1
TMULT_P0
4.66
4.57
4.47
4.37
4.28
4.18
4.08
3.99
3.89
3.79
3.69
3.60
3.50
3.40
3.31
3.21
3.11
3.02
2.92
2.82
2.72
2.63
2.53
2.43
2.34
2.24
2.14
2.05
1.95
1.85
1.75
1.66
1.56
1.46
1.37
1.27
8.50
8.33
8.16
7.99
7.82
7.65
7.48
7.31
7.14
6.97
6.80
6.63
6.46
6.29
6.12
5.95
5.78
5.61
5.44
5.27
5.10
4.93
4.76
4.59
4.42
4.25
4.08
3.91
3.74
3.57
3.40
3.23
3.06
2.89
2.72
2.55
10.36
10.15
9.95
9.74
9.53
9.33
9.12
8.91
8.70
8.50
8.29
8.08
7.88
7.67
7.46
7.26
7.05
6.84
6.63
6.43
6.22
6.01
5.81
5.60
5.39
5.19
4.98
4.77
4.56
4.36
4.15
3.94
3.74
3.53
3.32
3.12
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Input to Pin 8
Input to Pin 7
Input to Pin 6
Input to Pin 5
Input to Pin 4
Input to Pin 3
Input to Pin 2
Input to Pin 1
Input to Pin 0
DS031-3 (v3.5) November 5, 2007
Product Specification
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