R
Virtex-II Platform FPGAs: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Table 22: CLB Distributed RAM Switching Characteristics
Speed Grade
-5
Description
Symbol
-6
-4
Units
Sequential Delays
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
TSHCKO16
TSHCKO32
TSHCKOF5
1.63
1.97
1.77
1.79
2.17
1.94
2.05
2.49
2.23
ns, Max
ns, Max
ns, Max
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
TDS/TDH
TAS/TAH
0.53/–0.09
0.40/ 0.00
0.42/–0.01
0.58/–0.10
0.44/ 0.00
0.46/–0.01
0.67/–0.11
0.50/ 0.00
0.53/–0.01
ns, Min
ns, Min
ns, Min
F/G address inputs
SR input (WS)
TWES/TWEH
Clock CLK
Minimum Pulse Width, High
TWPH
TWPL
TWC
0.57
0.57
1.14
0.63
0.63
1.25
0.72
0.72
1.44
ns, Min
ns, Min
ns, Min
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
CLB Shift Register Switching Characteristics
Table 23: CLB Shift Register Switching Characteristics
Speed Grade
-5
Description
Sequential Delays
Symbol
-6
-4
Units
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
TREG
2.31
2.65
2.23
2.18
1.92
2.45
2.54
2.92
2.46
2.40
2.11
2.69
2.92
3.35
2.82
2.75
2.43
3.09
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TREG32
TREGXB
TREGYB
TCKSH
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
TREGF5
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
TSRLDS/TSRLDH
TWSS/TWSH
0.53/–0.07
0.19/–0.06
0.58/–0.08
0.21/–0.07
0.67/–0.09
0.24/–0.08
ns, Min
ns, Min
SR input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
TSRPH
TSRPL
0.57
0.57
0.63
0.63
0.72
0.72
ns, Min
ns, Min
DS031-3 (v3.5) November 5, 2007
Product Specification
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