R
Virtex-II Platform FPGAs: DC and Switching Characteristics
4. Record the time to V
.
Output Delay Measurements
MEAS
5. Compare the results of steps 2 and 4. The increase or
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table 17) to yield the actual worst-case propagation
delay (clock-to-input) of the PCB trace.
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See Virtex-II Platform FPGA User Guide for details.)
The propagation delay of the 4" trace is characterized sep-
arately and subtracted from the final measurement, and is
therefore not included in the generalized test setup shown in
Figure 1.
VREF
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at http://support.xil-
FPGA Output
RREF
inx.com/support/sw_ibis.htm.) Parameters V
, R
,
REF
REF
C
, and V
fully describe the test conditions for each
REF
MEAS
VMEAS
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
(voltage level at which
delay measurement is taken)
CREF
(probe capacitance)
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 19.
ds083-3_06a_092503
2. Record the time to V
.
MEAS
Figure 1: Generalized Test Setup
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
Table 19: Output Delay Measurement Methodology
(1)
IOSTANDARD
Attribute
RREF CREF
VMEAS VREF
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
(Ω)
1M
1M
1M
1M
1M
25
25
25
25
25
25
25
25
50
25
50
25
50
25
50
25
(pF)
(V)
(V)
LVTTL (all)
LVCMOS33
0
1.4
0
0
1.65
1.25
0.9
0
LVCMOS25
0
0
LVCMOS, 1.8V
LVCMOS18
0
0
LVCMOS, 1.5V
LVCMOS15
0
0.75
0.94
2.03
0.94
2.03
0.94
2.03
0.8
0
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
10(2)
0
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
10(2)
3.3
0
10(2)
10(2)
3.3
10(3)
PCI-X, 133 MHz, 3.3V
10(3)
3.3
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
GTL (Gunning Transceiver Logic)
GTL Plus
0
0
0
0
0
0
0
0
0
0
GTLP
1.0
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL_I
VREF
VREF
0.9
HSTL_II
HSTL, Class III
HSTL_III
HSTL, Class IV
HSTL_IV
0.9
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
HSTL_I_18
VREF
VREF
1.1
HSTL_II_18
HSTL_III_18
HSTL_IV_18
1.1
DS031-3 (v3.5) November 5, 2007
Product Specification
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