R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 19: Output Delay Measurement Methodology
(1)
IOSTANDARD
Attribute
RREF CREF
VMEAS VREF
Description
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
(Ω)
50
25
50
25
50
25
50
50
50
50
50
50
1M
50
1M
(pF)
0
(V)
(V)
0.9
0.9
1.25
1.25
1.5
1.5
0
SSTL18_I
SSTL18_II
VREF
VREF
VREF
VREF
VREF
VREF
0.94
2.03
VREF
VREF
VREF
VREF
1.2
0
SSTL, Class I, 2.5V
SSTL2_I
0
SSTL, Class II, 2.5V
SSTL2_II
0
SSTL, Class I, 3.3V
SSTL3_I
0
SSTL, Class II, 3.3V
SSTL3_II
0
AGP-2X/AGP (rising edge)
AGP-2X/AGP (falling edge)
LVDS_25
0
AGP-2X/AGP (Accelerated Graphics Port)
0
3.3
1.2
1.2
1.2
1.2
0
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
0
LVDSEXT_25
LVDS_33
0
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT, 3.3V
0
LVDSEXT_33
BLVDS_25
0
BLVDS (Bus LVDS), 2.5V
0
LDT (HyperTransport), 2.5V
LDT_25
0
VREF
1.23
0.6
0
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
LVPECL_33
0
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33, HSLVDCI_33
1M
0
1.65
0
LVDCI/HSLVDCI, 2.5V
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
HSTL_I_DCI, HSTL_II_DCI
HSTL_III_DCI, HSTL_IV_DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
HSTL_III_DCI_18, HSTL_IV_DCI_18
SSTL18_I_DCI, SSTL18_II_DCI
SSTL2_I_DCI, SSTL2_II_DCI
SSTL3_I_DCI, SSTL3_II_DCI
GTL_DCI
1M
1M
1M
50
50
50
50
50
50
50
50
50
0
0
0
0
0
0
0
0
0
0
0
0
1.25
0.9
0
0
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
0.75
VREF
0.9
0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI
HSTL, Class III & IV, with DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III & IV, 1.8V, with DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI
SSTL, Class I & II, 2.5V, with DCI
SSTL, Class I & II, 3.3V, with DCI
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
0.75
1.5
0.9
1.8
0.9
1.25
1.5
1.2
1.5
VREF
1.1
VREF
VREF
VREF
0.8
GTLP_DCI
1.0
Notes:
1.
CREF is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. Per PCI-X specifications.
DS031-3 (v3.5) November 5, 2007
Product Specification
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