R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Block SelectRAM Switching Characteristics
Table 28: Block SelectRAM Switching Characteristics
Speed Grade
Description
Sequential Delays
Symbol
-6
-5
-4
Units
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
ADDR inputs
TBCKO
2.10
2.31
2.65
ns, Max
TBACK/TBCKA
TBDCK/TBCKD
TBECK/TBCKE
TBRCK/TBCKR
TBWCK/TBCKW
0.29/ 0.00
0.29/ 0.00
0.95/–0.46
1.31/–0.71
0.57/–0.19
0.32/ 0.00
0.32/ 0.00
1.04/–0.50
1.44/–0.78
0.63/–0.21
0.36/ 0.00
0.36/ 0.00
1.20/–0.58
1.65/–0.90
0.72/–0.25
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
DIN inputs
EN input
RST input
WEN input
Clock CLK
CLKA to CLKB setup time for different ports
Minimum Pulse Width, High
Minimum Pulse Width, Low
TBCCS
TBPWH
TBPWL
1.0
1.0
1.0
ns, min
ns, Min
ns, Min
1.17
1.17
1.29
1.29
1.48
1.48
TBUF Switching Characteristics
Table 29: TBUF Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
-6
-5
-4
Units
IN input to OUT output
TIO
TOFF
TON
0.45
0.44
0.44
0.50
0.48
0.48
0.58
0.55
0.55
ns, Max
ns, Max
ns, Max
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
26
XILINX [ XILINX, INC ]
