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DS031 参数 Datasheet PDF下载

DS031图片预览
型号: DS031
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用:
文件页数/大小: 318 页 / 2407 K
品牌: XILINX [ XILINX, INC ]
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R
Virtex-II Platform FPGAs: DC and Switching Characteristics  
Table 27: Enhanced Pipelined Multiplier Switching Characteristics  
Speed Grade  
-5  
Description  
Setup and Hold Times Before/After Clock  
Data Inputs  
Symbol  
-6  
-4  
Units  
TMULIDCK/TMULCKID  
3.00/0.00  
0.72/0.00  
0.72/0.00  
3.45/0.00  
0.80/0.00  
0.80/0.00  
3.89/0.00  
0.86/0.00  
0.86/0.00  
ns, Max  
ns, Max  
ns, Max  
Clock Enable  
T
MULIDCK_CE/TMULCKID_CE  
Reset  
T
MULIDCK_RST/TMULCKID_RST  
Clock to Output Pin  
Clock to Pin 35  
Clock to Pin 34  
Clock to Pin 33  
Clock to Pin 32  
Clock to Pin 31  
Clock to Pin 30  
Clock to Pin 29  
Clock to Pin 28  
Clock to Pin 27  
Clock to Pin 26  
Clock to Pin 25  
Clock to Pin 24  
Clock to Pin 23  
Clock to Pin 22  
Clock to Pin 21  
Clock to Pin 20  
Clock to Pin 19  
Clock to Pin 18  
Clock to Pin 17  
Clock to Pin 16  
Clock to Pin 15  
Clock to Pin 14  
Clock to Pin 13  
Clock to Pin 12  
Clock to Pin 11  
Clock to Pin 10  
Clock to Pin 9  
TMULTCK1_P35  
TMULTCK1_P34  
TMULTCK1_P33  
TMULTCK1_P32  
TMULTCK1_P31  
TMULTCK1_P30  
TMULTCK1_P29  
TMULTCK1_P28  
TMULTCK1_P27  
TMULTCK1_P26  
TMULTCK1_P25  
TMULTCK1_P24  
TMULTCK1_P23  
TMULTCK1_P22  
TMULTCK1_P21  
TMULTCK1_P20  
TMULTCK1_P19  
TMULTCK1_P18  
TMULTCK1_P17  
TMULTCK1_P16  
TMULTCK1_P15  
TMULTCK1_P14  
TMULTCK1_P13  
TMULTCK1_P12  
TMULTCK1_P11  
TMULTCK1_P10  
TMULTCK1_P9  
TMULTCK1_P8  
TMULTCK1_P7  
TMULTCK1_P6  
TMULTCK1_P5  
TMULTCK1_P4  
TMULTCK1_P3  
TMULTCK1_P2  
TMULTCK1_P1  
TMULTCK1_P0  
3.05  
2.95  
2.85  
2.76  
2.66  
2.56  
2.47  
2.37  
2.27  
2.17  
2.08  
1.98  
1.88  
1.79  
1.69  
1.59  
1.50  
1.40  
1.30  
1.20  
1.11  
1.01  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
0.91  
3.25  
3.14  
3.04  
2.93  
2.82  
2.72  
2.61  
2.50  
2.40  
2.29  
2.18  
2.07  
1.97  
1.86  
1.75  
1.65  
1.54  
1.43  
1.33  
1.22  
1.11  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
1.00  
3.74  
3.61  
3.49  
3.37  
3.25  
3.12  
3.00  
2.88  
2.75  
2.63  
2.51  
2.38  
2.26  
2.14  
2.02  
1.89  
1.77  
1.65  
1.52  
1.40  
1.28  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
1.15  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
ns, Max  
Clock to Pin 8  
Clock to Pin 7  
Clock to Pin 6  
Clock to Pin 5  
Clock to Pin 4  
Clock to Pin 3  
Clock to Pin 2  
Clock to Pin 1  
Clock to Pin 0  
DS031-3 (v3.5) November 5, 2007  
Product Specification  
www.xilinx.com  
Module 3 of 4  
25  
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