R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Clock Distribution Switching Characteristics
Table 20: Clock Distribution Switching Characteristics
Speed Grade
Description
Symbol
-6
-5
-4
Units
Global Clock Buffer I input to O output
TGIO
0.47
0.52
0.59
ns, Max
Global Clock Buffer S input Setup/Hold
to I1 an I2 inputs
TGSI/TGIS
0.55/ 0
0.61/ 0
0.70/ 0
ns, Max
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 16 in Module 2). The values listed below
are worst-case. Precise values are provided by the timing analyzer.
Table 21: CLB Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
-6
-5
-4
Units
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
TILO
TIF5
0.35
0.57
0.76
0.36
0.26
0.26
0.35
0.39
0.63
0.83
0.39
0.28
0.28
0.38
0.44
0.72
0.95
0.45
0.32
0.32
0.44
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TIF5X
TIFXY
TINAFX
TINBFX
TSOPSOP
Incremental delay routing through transparent latch to
XQ/YQ outputs
TIFNCTL
0.41
0.45
0.51
ns, Max
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
BX/BY inputs
TCKO
0.45
0.54
0.50
0.59
0.57
0.68
ns, Max
ns, Max
TCKLO
TDICK/TCKDI
0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, Min
0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, Min
0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, Min
0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, Min
0.21/–0.02 0.23/–0.03 0.26/–0.03 ns, Min
DY inputs
T
DYCK/TCKDY
TDXCK/TCKDX
TCECK/TCKCE
TSRCK/TSCKR
DX inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
TCH
TCL
0.61
0.61
0.67
0.67
0.77
0.77
ns, Min
ns, Min
Minimum Pulse Width, SR/BY inputs (asynchronous)
TRPW
TRQ
0.61
1.06
820
0.67
1.17
750
0.77
1.34
650
ns, Min
ns, Max
MHz
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (MHz) (for export control)
FTOG
DS031-3 (v3.5) November 5, 2007
Product Specification
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Module 3 of 4
20
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