R
Virtex-II Platform FPGAs: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 18 shows the test setup parameters used for measuring Input standard adjustments (see Table 15, page 11).
Table 18: Input Delay Measurement Methodology
IOSTANDARD
Attribute
VMEAS VREF
(1,2)
(1,2)
VL
VH
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
(1,4,5)
(1,3,5)
LVTTL
LVCMOS33
0
0
0
0
0
3.0
1.4
–
3.3
2.5
1.8
1.5
1.65
1.25
0.9
–
LVCMOS25
–
LVCMOS, 1.8V
LVCMOS18
–
LVCMOS, 1.5V
LVCMOS15
0.75
–
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI33_3
Per PCI Specification
Per PCI Specification
Per PCI-X Specification
–
PCI66_3
–
PCI-X, 133 MHz, 3.3V
PCIX
–
GTL (Gunning Transceiver Logic)
GTL Plus
GTL
V
V
V
V
V
V
– 0.2
V
V
V
V
V
V
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 1.00
+ 0.75
+ 0.5
+
V
V
V
V
V
V
V
V
V
0.80
1.0
0.75
0.90
0.90
1.08
1.5
1.25
0.90
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
GTLP
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
– 1.00
– 0.75
– 0.5
–
HSTL (High-Speed Transceiver Logic), Class I & II
HSTL, Class III & IV
HSTL_I, HSTL_II
HSTL_III, HSTL_IV
HSTL_I_18, HSTL_II_18
HSTL_III_18, HSTL_IV_18
SSTL3_I, SSTL3_II
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V
SSTL, Class I & II, 2.5V
V
V
V
REF
REF
REF
REF
V
SSTL, Class I & II, 1.8V
V
V
REF
REF
V
V
AGP
Spec
REF
REF
AGP-2X/AGP (Accelerated Graphics Port)
AGP
V
REF
(0.2 xV
)
(0.2xV
)
CCO
CCO
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
LVDS_25
LVDS_33
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
1.6 – 0.3
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
1.6 + 0.3
1.2
1.2
1.2
1.2
0.6
0.6
1.6
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT, 3.3V
LVDSEXT_25
LVDSEXT_33
ULVDS_25
LDT_25
ULVDS (Ultra LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
Notes:
LVPECL_33
1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters
for all other DCI standards are the same as for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values
listed are typical. See Virtex-II Platform FPGA User Guide for min/max specifications.
4. Input voltage level from which measurement starts.
5. Note that this is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1.
DS031-3 (v3.5) November 5, 2007
Product Specification
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