R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Speed Grade
-5 -4
IOSTANDARD
Attribute
Timing
Parameter
Description
-6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
HSTL_II_18
HSTL_III_18
HSTL_IV_18
SSTL18_I
TOHSTL_II_18
TOHSTL_III_18
TOHSTL_IV_18
TOSSTL18_I
–0.17 –0.18 –0.20
–0.16 –0.16 –0.18
–0.39 –0.40 –0.44
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
0.20
–0.05 –0.05 –0.06
0.21 0.22 0.24
–0.15 –0.16 –0.18
0.29 0.30 0.33
0.20
0.22
SSTL18_II
TOSSTL18_II
TOSSTL2_I
SSTL, Class I, 2.5V
SSTL2_I
SSTL, Class II, 2.5V
SSTL2_II
TOSSTL2_II
SSTL, Class I, 3.3V
SSTL3_I
TOSSTL3_I
SSTL, Class II, 3.3V
SSTL3_II
TOSSTL3_II
–0.05 –0.05 –0.05
–0.27 –0.28 –0.31
AGP-2X/AGP (Accelerated Graphics Port)
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
AGP
TOAGP
LVDCI_33
TOLVDCI_33
0.74
0.78
0.84
1.82
0.12
0.03
0.42
1.20
1.82
1.05
0.78
0.74
0.77
0.80
0.87
1.88
0.12
0.03
0.43
1.23
1.88
1.08
0.80
0.77
0.84
0.88
0.95
2.06
0.13
0.03
0.48
1.36
2.06
1.24
0.88
0.84
LVDCI_25
TOLVDCI_25
LVDCI, 1.8V
LVDCI_18
TOLVDCI_18
LVDCI, 1.5V
LVDCI_15
TOLVDCI_15
LVDCI, 3.3V, Half-Impedance
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI, 1.8V
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
GTL_DCI
TOLVDCI_DV2_33
TOLVDCI_DV2_25
TOLVDCI_DV2_18
TOLVDCI_DV2_15
TOHSLVDCI_15
TOHSLVDCI_18
TOHSLVDCI_25
TOHSLVDCI_33
TOGTL_DCI
HSLVDCI, 2.5V
HSLVDCI, 3.3V
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
–0.31 –0.32 –0.35
–0.15 –0.16 –0.17
GTLP_DCI
TOGTLP_DCI
TOHSTL_I_DCI
TOHSTL_II_DCI
TOHSTL_III_DCI
TOHSTL_IV_DCI
TOHSTL_I_DCI_18
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
0.23
0.06
0.23
0.06
0.26
0.07
HSTL, Class III, with DCI
–0.17 –0.18 –0.20
–0.46 –0.47 –0.52
HSTL, Class IV, with DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
SSTL, Class I, 3.3V, with DCI
SSTL, Class II, 3.3V, with DCI
0.05
0.05
0.06
TOHSTL_II_DCI_18 –0.03 –0.03 –0.03
TOHSTL_III_DCI_18 –0.14 –0.14 –0.16
TOHSTL_IV_DCI_18 –0.41 –0.42 –0.47
TOSSTL18_I_DCI
TOSSTL18_II_DCI
TOSSTL2_I_DCI
TOSSTL2_II_DCI
TOSSTL3_I_DCI
TOSSTL3_II_DCI
0.36
0.06
0.12
0.37
0.06
0.13
0.40
0.07
0.14
–0.10 –0.10 –0.11
0.15
0.08
0.16
0.08
0.17
0.09
DS031-3 (v3.5) November 5, 2007
Product Specification
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