W90N745CD/W90N745CDG
HSUART Time Out Register (HSUART_TOR)
REGISTER
OFFSET R/W
DESCRIPTION
RESET VALUE
0x1C
R/W
0x0000_0000
HSUART_TOR
Time Out Register
31
23
15
30
29
21
13
5
28
20
27
26
18
10
2
25
24
16
8
Reserved
22
14
6
19
11
3
17
9
Reserved
12
Reserved
7
4
1
0
TOIE
TOIC
BITS
DESCRIPTIONS
[31:8]
Reserved
TOIE
-
Time Out Interrupt Enable
[7]
The feature of receiver time out interrupt is enabled only when TOR [7] =
IER[0] = 1.
Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock = baud
rate) whenever the RX FIFO receives a new data word. Once the content
of time out counter (TOUT_CNT) is equal to that of time out interrupt
comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if
TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears
Irpt_TOUT.
[6:0]
TOIC
Publication Release Date: September 22, 2006
- 287 -
Revision A2
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