W90N745CD/W90N745CDG
31
nDBGACK_EN
23
30
CEN
22
29
IE
28
27
19
11
3
26
CRST
18
25
CACT
17
24
Reserved
16
MODE[1:0]
21
20
Reserved
15
7
14
6
13
5
12
10
2
9
1
8
0
Reserved
4
PRESCALE[7:0]
BITS
DESCRIPTIONS
ICE debug mode acknowledge enable
0 = When DBGACK is high, the TIMER counter will be held
[31]
[30]
nDBGACK_EN
CEN
1 = No matter DBGACK is high or not, the TIMER counter will not
be held
Counter Enable
0 = Stops/Suspends counting
1 = Starts counting
Interrupt Enable
0 = Disable TIMER Interrupt.
[29]
IE
1 = Enable TIMER Interrupt. If timer interrupt is enabled, the timer
asserts its interrupt signal when the associated counter
decrements to zero.
Timer Operating Mode
MODE
Timer Operating Mode
00
The timer is operating in the one-shot mode. The
associated interrupt signal is generated once (if IE is
enabled) and CEN is automatically cleared then.
01
10
The timer is operating in the periodic mode. The
associated interrupt signal is generated periodically
(if IE is enabled).
[28:27]
MODE
The timer is operating in the toggle mode. The
interrupt signal is generated periodically (if IE is
enabled). And the associated signal (tout) is
changing back and forth with 50% duty cycle.
11
Reserved.
Publication Release Date: September 22, 2006
- 289 -
Revision A2
WINBOND [ WINBOND ]
