W90N745CD/W90N745CDG
31
23
15
30
22
14
29
21
13
28
Reserved
20
Reserved
12
Reserved
27
19
11
26
18
10
25
17
9
24
16
8
7
6
5
4
3
2
1
0
WLS
DLAB
BCB
SPE
EPE
PBE
NSB
HSUART Modem Control Register (HSUART_MCR)
REGISTER
OFFSET R/W
0x10 R/W
DESCRIPTION
Modem Control Register (Optional)
RESET VALUE
0x0000_0000
HSUART_MCR
31
23
15
7
30
29
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
Reserved
Reserved
Reserved
22
14
6
21
13
5
17
9
1
0
RTS
Reserved
Reserved
LBME
Reserved
BITS
DESCRIPTIONS
[31:5]
Reserved
-
Loop-back Mode Enable
0 = Disable
1 = When the loop-back mode is enabled, the following signals are connected
internally:
[4]
LBME
SOUT connected to SIN and SOUT pin fixed at logic 1
RTS# connected to CTS# and RTS# pin fixed at logic 1
Publication Release Date: September 22, 2006
- 283 -
Revision A2
WINBOND [ WINBOND ]
