W90N745CD/W90N745CDG
HSUART Modem Status Register (HSUART_MSR)
REGISTER
OFFSET R/W
0x18
DESCRIPTION
RESET VALUE
HSUART_MSR
R
MODEM Status Register (Optional)
0x0000_0000
31
23
15
7
30
22
14
6
29
28
Reserved
20
Reserved
12
Reserved
27
19
11
3
26
18
10
25
17
9
24
16
8
21
13
5
4
2
1
0
Reserved
Reserved
CTS#
DCTS
BITS
DESCRIPTIONS
[31:5]
Reserved
CTS#
-
Complement version of clear to send (CTS#) input
(This bit is selected by IP)
[4]
[3:1]
Reserved
-
CTS# State Change
(This bit is selected by IP)
[0]
DCTS
This bit is set whenever CTS# input has changed state, and it will be reset if
the CPU reads the MSR.
Whenever any of MSR [0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
- 286 -
WINBOND [ WINBOND ]
