W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
[3:2]
Reserved
RTS#
-
Complement version of RTS# (Request-To-Send) signal
Writing 0x00 to MCR, RTS# bit are set to logic 1’s;
Writing 0x0f to MCR, RTS# bit are reset to logic 0’s.
[1]
[0]
Reserved
-
HSUART Line Status Control Register (HSUART_LSR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
0x14
0x6060_6060
HSUART_LSR
R
Line Status Register
31
23
15
30
29
21
13
28
27
26
18
10
25
17
9
24
16
8
Reserved
22
14
20
19
11
Reserved
12
Reserved
7
6
5
4
3
2
1
0
ERR_RX
TE
THRE
BII
FEI
PEI
OEI
RFDR
BITS
DESCRIPTIONS
[31:8]
Reserved
ERR_RX
RX FIFO Error
0 = RX FIFO works normally
[7]
1 = There is at least one parity error (PE), framing error (FE), or break
indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the
LSR and if there are no subsequent errors in the RX FIFO.
Transmitter Empty
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter
Shift Register (TSR) are not empty.
[6]
TE
1 = Both THR and TSR are empty.
- 284 -
WINBOND [ WINBOND ]
