W90N745CD/W90N745CDG
HSUART Line Control Register (HSUART_LCR)
REGISTER
OFFSET R/W
DESCRIPTION
RESET VALUE
0x0C
R/W Line Control Register
0x0000_0000
HSUART_LCR
BITS
DESCRIPTIONS
[31:8]
Reserved
DLAB
-
Divider Latch Access Bit
[7]
[6]
0 = It is used to access RBR, THR or IER.
1 = It is used to access Divisor Latch Registers {DLL, DLM}.
Break Control Bit
When this bit is set to logic 1, the serial data output (SOUT) is
forced to the Spacing State (logic 0). This bit acts only on
SOUT and has no effect on the transmitter logic.
Stick Parity Enable
BCB
SPE
0 = Disable stick parity
[5]
[4]
[3]
[2]
1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is
0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This
bit has effect only when bit 3 (parity bit enable) is set.
Even Parity Enable
0 = Odd number of logic 1’s are transmitted or checked in
the data word and parity bits.
1 = Even number of logic 1’s are transmitted or checked in
the data word and parity bits.
EPE
PBE
NSB
This bit has effect only when bit 3 (parity bit enable) is set.
Parity Bit Enable
0 = Parity bit is not generated (transmit data) or checked
(receive data) during transfer.
1 = Parity bit is generated or checked between the "last data
word bit" and "stop bit" of the serial data.
Number of “STOP bit”
0= One “ STOP bit” is generated in the transmitted data
1= One and a half “ STOP bit” is generated in the transmitted
data when 5-bit word length is selected;
Two “ STOP bit” is generated when 6-, 7- and 8-bit word length
is selected.
Word Length Select
WLS[1:0]
Character length
5 bits
00
[1:0]
WLS
01
10
6 bits
7 bits
11
8 bits
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