W90N745CD/W90N745CDG
Interrupt Control Functions
INTERRUPT RESET
INTERRUPT SOURCE
IIR [3:0]
PRIORITY
INTERRUPT TYPE
CONTROL
---1
--
None
None
error,
--
Overrun
parity
Receiver Line Status
(Irpt_RLS)
0110
0100
Highest
Second
error, framing error, or Reading the LSR
break interrupt
Receiver FIFO drops
Receiver FIFO threshold
below the threshold
Received Data
Available (Irpt_RDA)
level is reached
level
Receiver FIFO is non-
empty and no activities
Receiver FIFO Time- are occurred in the
1100
Second
Reading the RBR
out (Irpt_TOUT)
receiver FIFO during the
TOR
defined
time
duration
Reading the IIR (if
holding source of interrupt is
Irpt_THRE) or
Transmitter Holing
Register Empty
(Irpt_THRE)
Transmitter
register empty
0010
0000
Third
writing into the THR
Reading the MSR
MODEM Status
(Irpt_MOS)
The CTS bits are changing
state .
Fourth
(optional)
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550.
HSUART FIFO Control Register (HSUART_FCR)
REGISTER
OFFSET R/W
0x08
DESCRIPTION
RESET VALUE
W
FIFO Control Register
Undefined
HSUART_FCR
31
23
15
7
30
22
14
6
29
28
20
12
4
27
19
11
26
25
17
9
24
16
8
Reserved
Reserved
Reserved
21
13
5
18
10
3
2
1
0
RFITL
DMS
TFR
RFR
FME
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