W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:8]
Reserved
-
RX FIFO Interrupt (Irpt_RDA) Trigger Level
RFITL
0000
0001
0010
0011
0100
0101
0110
others
Irpt_RDA Trigger Level (Bytes)
01
04
08
14
30
46
62
62
[7:4]
RFITL
DMA Mode Select
[3]
[2]
DMS
TFR
The DMA function is not implemented in this version.
TX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO.
The TX FIFO becomes empty (TX pointer is reset to 0) after such reset.
This bit is returned to 0 automatically after the reset pulse is generated.
RX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO.
The RX FIFO becomes empty (RX pointer is reset to 0) after such reset.
This bit is returned to 0 automatically after the reset pulse is generated.
[1]
[0]
RFR
FME
FIFO Mode Enable
Because UART is always operating in the FIFO mode, writing this bit has
no effect while reading always gets logical one. This bit must be 1 when
other FCR bits are written to; otherwise, they will not be programmed.
Publication Release Date: September 22, 2006
- 281 -
Revision A2
WINBOND [ WINBOND ]
