W90N745CD/W90N745CDG
31
23
15
30
22
14
6
29
21
13
5
28
Reserved
20
Reserved
12
Reserved
27
19
11
3
26
18
10
2
25
17
9
24
16
8
7
4
1
0
FMES
RFTLS
DMS
IID
NIP
BITS
DESCRIPTIONS
[31:8]
Reserved
FMES
-
FIFO Mode Enable Status
This bit indicates whether the FIFO mode is enabled or not. Since the
FIFO mode is always enable, this bit always shows the logical 1 when
CPU is reading this register.
[7]
RX FIFO Threshold Level Status
These bits show the current setting of receiver FIFO threshold level
(RTHO). The meaning of RTHO is defined in the following FCR
description.
[6:5]
[4]
RFTLS
DMS
DMA Mode Select
The DMA function is not implemented in this version. When reading IIR,
the DMS is always returned 0.
Interrupt Identification
[3:1]
[0]
IID
The IID together with NIP indicates the current interrupt request from
UART.
No Interrupt Pending
NIP
There is no pending interrupt.
Publication Release Date: September 22, 2006
- 279 -
Revision A2
WINBOND [ WINBOND ]
