W90N745CD/W90N745CDG
BITS
[7]
DESCRIPTIONS
Divider Latch Access Bit
DLAB
BCB
0 = It is used to access RBR, THR or IER.
1 = It is used to access Divisor Latch Registers {DLL, DLM}
Break Control Bit
[6]
[5]
When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing
State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic.
Stick Parity Enable
0 = Disable stick parity
SPE
EPE
1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as
a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit
enable) is set.
Even Parity Enable
0 = Odd number of logic 1’s are transmitted or checked in the data word and
parity bits.
[4]
1 = Even number of logic 1’s are transmitted or checked in the data word and
parity bits.
This bit has effect only when bit 3 (parity bit enable) is set.
Parity Bit Enable
0 = Parity bit is not generated (transmit data) or checked (receive data) during
transfer.
PBE
NSB
[3]
[2]
1 = Parity bit is generated or checked between the "last data word bit" and "stop bit"
of the serial data.
Number of “STOP bit”
0= One “ STOP bit” is generated in the transmitted data
1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word
length is selected;
Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected.
Word Length Select
WLS[1:0]
Character length
00
01
10
11
5 bits
6 bits
7 bits
8 bits
WLS
[1:0]
Publication Release Date: September 22, 2006
Revision A2
- 269 -
WINBOND [ WINBOND ]
