W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
-
[31:6]
Reserved
DSR#
Complement version of data set ready (DSR#) input
(This bit is selected by IP)
[5]
[4:2]
Reserved
-
DSR# State Change (This bit is selected by IP)
[1]
[0]
DDSR
This bit is set whenever DSR# input has changed state, and it will be reset
if the CPU reads the MSR.
Reserved
-
Whenever any of MSR [3:0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
UART Time Out Register (UART_TOR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
UART_TOR
0x1C
R/W Time Out Register
0x0000_0000
31
23
15
30
22
14
6
29
21
13
5
28
Reserved
20
Reserved
12
Reserved
27
19
11
3
26
18
10
2
25
17
9
24
16
8
7
4
1
0
TOIE
TOIC
BITS
DESCRIPTIONS
-
[31:8] Reserved
Time Out Interrupt Enable
The feature of receiver time out interrupt is enabled when TOR [7] = IER[0] = 1.
[7]
TOIE
Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock = baud
rate) whenever the RX FIFO receives a new data word. Once the content of
time out counter (TOUT_CNT) is equal to that of time out interrupt
comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if
TOR [7] = IER [0] = 1. A new incoming data word or RX FIFO empty clears
Irpt_TOUT.
[6:0]
TOIC
Publication Release Date: September 22, 2006
- 273 -
Revision A2
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