W90N745CD/W90N745CDG
BITS
[7:0]
DESCRIPTIONS
Baud Rate Divider (High Byte)
The high byte of the baud rate divider
This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows
Baud Rate = Crystal Clock / {16 * [Divisor + 2]}
Note: This definition is different from 16550
UART Interrupt Identification Register (UART_IIR)
REGISTER OFFSET
R/W
DESCRIPTION
RESET VALUE
R
0x08
Interrupt Identification Register
0x8181_8181
UART_IIR
31
30
29
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
23
15
22
14
6
21
13
5
Reserved
Reserved
7
2
1
0
FMES
RFTLS
DMS
IID
NIP
BITS
[7]
DESCRIPTIONS
FIFO Mode Enable Status
This bit indicates whether the FIFO mode is enabled or not. Since the FIFO
mode is always enabling, this bit always shows the logical 1 when CPU is
reading this register.
FMES
RX FIFO Threshold Level Status
RFTLS
DMS
[6:5]
[4]
These bits show the current setting of receiver FIFO threshold level (RTHO).
The meaning of RTHO is defined in the following FCR description.
DMA Mode Select
The DMA function is not implemented in this version. When reading IIR, the
DMS is always returned 0.
Interrupt Identification
IID
[3:1]
[0]
The IID together with NIP indicates the current interrupt request from UART
No Interrupt Pending
NIP
There is no pending interrupt.
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