W90N745CD/W90N745CDG
UART Divider Latch (Low Byte) Register (UART_DLL)
REGISTER
UART_DLL
OFFSET
R/W
DESCRIPTION
RESET VALUE
R/W
0x00
Divisor Latch Register (LS) (DLAB = 1)
0x0000_0000
31
23
15
7
30
22
14
6
29
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
21
13
5
Reserved
Reserved
1
0
Baud Rate Divider (Low Byte)
BITS
DESCRIPTIONS
Baud Rate Divider (Low Byte)
[7:0]
The low byte of the baud rate divider
UART Divisor Latch (High Byte) Register (UART_DLM)
REGISTER OFFSET
R/W
DESCRIPTION
RESET VALUE
R/W
UART_DLM
0x04
Divisor Latch Register (MS) (DLAB = 1)
0x0000_0000
31
30
29
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
23
15
7
22
14
6
21
13
5
Reserved
Reserved
1
0
Baud Rate Divider (High Byte)
Publication Release Date: September 22, 2006
Revision A2
- 265 -
WINBOND [ WINBOND ]
