W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
Parity Error Indicator
This bit is set to logic 1 whenever the received character does not have a
valid "parity bit", and is reset whenever the CPU reads the contents of the
LSR.
[2]
PEI
Overrun Error Indicator
An overrun error will occur only after the RX FIFO is full and the next
character has been completely received in the shift register. The character
in the shift register is overwritten, but it is not transferred to the RX FIFO.
OE is indicated to the CPU as soon as it happens and is reset whenever
the CPU reads the contents of the LSR.
[1]
[0]
OEI
RX FIFO Data Ready
RFDR
0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not
suggested)
UART Modem Status Register (UART_MSR)
REGISTER
OFFSET
R/W
DESCRIPTION
RESET VALUE
UART_MSR
0x18
R
MODEM Status Register (Optional)
0x0000_0000
31
23
15
30
22
14
29
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
21
13
7
6
5
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DSR#
DDSR
- 272 -
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