W90N745CD/W90N745CDG
Table 6.10.6 Interrupt Control Functions
INTERRUPT
TYPE
INTERRUPT RESET
CONTROL
IIR [3:0]
PRIORITY
INTERRUPT SOURCE
---1
--
None
None
--
Overrun error, parity error,
framing error, or break Reading the LSR
interrupt
Receiver Line
Status (Irpt_RLS)
0110
0100
Highest
Second
Received Data
Available
(Irpt_RDA)
Receiver FIFO drops
below the threshold
level
Receiver FIFO threshold
level is reached
Receiver FIFO is non-empty
and no activities are
occurred in the receiver Reading the RBR
FIFO during the TOR
Receiver FIFO
Time-out
(Irpt_TOUT)
1100
Second
defined time duration
Transmitter
Holing Register
Empty
Reading the IIR (if
Transmitter holding register source of interrupt is
0010
0000
Third
empty
Irpt_THRE) or writing
into the THR
(Irpt_THRE)
The CTS, DSR, or DCD bits
MODEM Status are changing state or the RI Reading the MSR
Fourth
(Irpt_MOS)
bit is changing from high to
low.
(optional)
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550
UART FIFO Control Register (UART_FCR)
REGISTER
OFFSET
R/W
DESCRIPTION
FIFO Control Register
RESET VALUE
W
UART_FCR
0x08
Undefined
31
23
15
7
30
22
14
6
29
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
21
13
5
Reserved
Reserved
2
1
0
RFITL
RESERVED
DMS
TFR
RFR
FME
Publication Release Date: September 22, 2006
Revision A2
- 267 -
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